Nanofabrication process tracker

Pick a step to read the tooling, chemicals and procedure straight from the SOP.·4-inch Si → NbTiN → patterning → 3×3 blocks → measurement

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Oct 13, 2026, 01:10 AM

reporting week

Oct 13, 2026

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Oct 20, 2026

records loaded

33 wafers · 6 blocks · 24 cooldowns

wafers tracked

6 diced out to blocks

wafers in fab

still on the wafer-level route

blocks in fab

0 finalized

blocks measured

DC or gain data taken

steps documented

6/34

written up in the SOP

01
Substrate cleaning
wafer4-inch high-resistivity Si: pre-sputter, RCA-1, HF dip
02
NbTiN deposition
waferPlassys sputter, 70-30 target, anneal at 650 °C
03
Wafer patterning
waferPMGI SF7 + S1811, MLA, develop, 50 nm Al, lift off
04
Dicing to blocks
waferSPR90 protection, DISCO saw, overnight Remover PG
05
Main layer
blockZEP + JEOL EBL, 35 nm Al, lift off, RIE etch, Al strip
06
Tc protection & pads
blockTwo MLA lithography rounds with 50 nm Al each
07
Ground layers
blocka-Si / NbN with AJA sputter, pattern and etch at G2N
08
Dicing & measurement
blockProtect, dice, clean, then DC and gain measurement

step 1.2

RCA-1 clean

Tool ACIDBASEnonHF · NEMO “Wetbenches”

PPE

Full wetbench PPE, donned in SOP order; green gloves for bottle handling only

Key parameters

Solution: DI : NH4OH : H2O2 = 5 : 1 : 1 (500 / 100 / 100 mL)
Bath temperature: 75–80 °C
Soak: 10 min
Rinse: 3 trays, 60–80 s each (4–5 min total)

Materials & chemicals

·High-resistivity Si wafer
·NH4OH, H2O2
·1 beaker + 3 DI rinse trays (QuantumCore box, not community)
·PTFE-coated thermometer, graduated cylinders
·Dedicated hotplate (cabinet under the fumehood)

Procedure

1Bring supplies and chemicals — also bring HF now, it is needed in 1.3.
2Inspect and DI-rinse the beakers and trays; set the hotplate to 300 °C for fast heat-up.
3Pour 500 mL DI, then add 100 mL NH4OH — always add acid to water.
4At 80 °C add 100 mL H2O2 with the thermometer fully immersed.
5Soak the wafer on the carrier for 10 min, holding 75–80 °C.
6Overflow-rinse in 3 DI trays, N2 blow dry front and back, move quickly to the HF bench.

At this step (1)

WA no deposition yet · room temp

glyph key

How to read a wafer or block mark

shape

disc with flat = 4-inch wafer, ticks = SD / LD deposition
square = 3×3 block diced from that wafer

ring colour — thermal history

room temperature
annealed
annealed 650 °C

sweep — route progress

15% of the route done
45% of the route done
80% of the route done
route complete

centre — measurement outcome

measured
partially measured
not measured

filters

Narrow the tree and register by glyph state

33/33 wafers · 6/6 blocks

temperature

route progress

measurement outcome

deposition length

branching tree

Wafer progress, expanding into blocks and patterns

Expand a wafer to walk its route; at dicing the branch splits into the 3×3 blocks cut from it, each with its own block-level steps and pattern.

No blocks diced from this wafer yet.

Coated wafers

wafer	batch	NbTiN	dep	anneal	deposited	status	WATLab samples	notes
W0A	Process Wafer	—	—	RT	—	Coated Al	—
W0B	Process Wafer	—	—	RT	—	Coated NbTiN	—
W0C	Process Wafer	—	—	RT	—	Not started	—
W0D	Process Wafer	—	—	RT	—	Not started	—
WA	Category 2	—	—	RT	—	In progress	—
WB	—	—	—	RT	—	Not started	—
WC	—	—	—	RT	—	Not started	—
WD	—	—	—	RT	—	Not started	—
WE	Category 3	—	—	RT	—	Not started	—
WF	20nm	20 nm	LD	RT	2026-04-23	Diced	—
WG	8nm	8 nm	LD	RT	2026-06-01	Diced	—
WH	17nm	17 nm	SD	RT	2026-04-02	Diced	—
WI	8nm	8 nm	LD	RT	2026-07-08	Diced	—
WJ	8nm	8 nm	SD	RT	2026-07-08	Coated NbTiN	—
WK	14nm	14 nm	LD	RT	2026-04-13	Diced	—
WL	8nm	8 nm	LD	RT	2026-07-14	Coated NbTiN	—
WM	8nm	8 nm	SD	RT	2026-07-15	Coated NbTiN	—
WN	10nm	10 nm	LD	RT	2026-07-22	Coated NbTiN	—
WO	14nm	14 nm	SD	RT	2026-04-13	Diced	—
WP	10nm	10 nm	LD	RT	2026-07-29	Coated NbTiN	—
WQ	20nm	20 nm	LD	RT	2026-07-30	Coated NbTiN	—
WR	8nm	8 nm	LD	RT	2026-08-04	Coated NbTiN	—
WS	20nm	20 nm	LD	RT	2026-08-05	Not started	—	University Wafer, DC error 2 sec
WT	10nm	10 nm	LD	RT	2026-08-06	Coated NbTiN	—	University Wafers
WU	8nm	8 nm	LD	RT	2026-08-07	Coated NbTiN	—	TOPSIL Wafer
WV	20nm	20 nm	LD	RT	2026-08-10	Coated NbTiN	—	TOPSIL Wafer
WW	10nm	10 nm	LD	RT	2026-08-11	Coated NbTiN	—	TOPSIL Wafer- DC bias error 3 sec
WX	8nm	8 nm	LD	RT	2026-08-13	Coated NbTiN	—	TOPSIL Wafer
WY	8nm	8 nm	LD	RT	2026-09-03	Coated NbTiN	—	TOPSIL Wafer
WZ	20nm	20 nm	LD	RT	2026-09-08	Coated NbTiN	—	TOPSIL Wafer
WAA	10nm	10 nm	LD	RT	2026-09-14	Coated NbTiN	—	TOPSIL Wafer
WAB	20nm	20 nm	LD	RT	2026-09-15	Coated NbTiN	—	TOPSIL Wafer
WAC	8nm	8 nm	LD	RT	2026-09-21	Coated NbTiN	—	TOPSIL Wafer

Where every wafer and block sits right now

Substrate cleaning

NbTiN deposition

Wafer patterning

Dicing to blocks

Main layer

Tc protection & pads

Ground layers

Dicing & measurement

How to read a wafer or block mark

Narrow the tree and register by glyph state

Wafer progress, expanding into blocks and patterns

Coated wafers